1. Field of the Invention
The invention disclosed in the present specification relates to the construction of a thin-film transistor and a method for its fabrication.
2. Description of the Related Art
Thin-film transistors (generally termed TFTs) which employ thin-film semiconductors formed on a substrate which has an insulating surface, such as a glass substrate, are known. These thin-film transistors are used in various types of integrated circuit. There are in particular known examples in which they are arranged at each pixel portion of an active matrix-type liquid crystal display device, and are used for switching the pitch element.
Known types of thin-film semiconductor include amorphous silicon films and crystalline silicon films. Amorphous silicon films have the feature that they have excellent productivity since film formation is simple, but there is the problem that their electrical properties are low, and the properties of the resulting thin-film transistors are low. On the other hand, crystalline silicon films have the feature that thin-film transistors which have high properties can be obtained. However, since at present it is not possible to obtain monocrystal silicon films, the resulting films inevitably have a multi-crystalline structure or a fine crystalline structure (the general term for these is crystalline silicon films).
FIG. 2(A) shows an example of a typical thin-film transistor. FIG. 2 shows that a silicon oxide film 202 forms a surface on a glass substrate 201, and that on this surface there is an active layer which consists of an n-type source region 203, an effectively intrinsic (I-type) channel-forming region 204, and an n-type drain region 205, and that there are further a gate insulating film 206, a gate electrode 207, an inter-layer insulating film 208, a source electrode 209 and a drain electrode 210.
In thin-film transistors which employ such crystalline silicon films, the presence of an OFF current (also known as a leak current) is a significant problem. The OFF current is a phenomenon whereby when the n-channel type thin-film transistor shown in FIG. 2, for example, is in the OFF state, if a negative voltage is applied to the gate electrode 207, then a current flows between the channel-forming region 204 and the drain region 205. With the n-channel type thin-film transistor in the OFF state, if a negative voltage is applied to the gate electrode 207 then the portion of the channel-forming region 204 which is in contact with the gate insulating film 206 becomes a p-type region. Thus if the thin-film semiconductor which constitutes the active layer (in which the source/drain regions and channel-forming regions are formed) is a monocrystal, then a pn junction forms between the source and the drain, and no large current flows between the source and the drain. However, if the thin-film semiconductor constituting the active layer has a multi-crystalline structure or a fine-crystalline structure then movement of carriers will inevitably occur across crystal grain boundaries due to the high electric field which forms between the source region or the drain region and the channel-forming region. As a result, the OFF current is relatively large.
A known technique which is used to reduce the abovementioned OFF current is to adopt an LDD structure or an offset gate structure. These structures aim to reduce the OFF current by arranging that electric fields are not concentrated at the boundaries between the source region or the drain region and the channel-forming region, or in the vicinity thereof.
According to the research of the inventors, the abovementioned LDD structure and offset gate structure are certainly effective in reducing the OFF current, but it was discovered that it is not possible to obtain a substantially large improvement. Thus the dependence of the OFF current on various parameters was investigated by varying the various parameters. As a result it was discovered that there is little variation in the OFF current even if the width of the active layer is varied. FIG. 2(B) shows the approximate form of the active layer. In FIG. 2(B), 21 is a source region, 22 is a channel-forming region and 23 is a drain region. Further, W is the width of the active layer and L is the length of the active layer.
Firstly, when the width W of the active layer was varied, no noticeable variation in the value of the OFF current was seen. If carrier movement, which is the cause of the OFF current, were occurring over the whole cross-section of the active layer then one would expect to see a variation in the value of the OFF current as the width W of the active layer is varied. This is because by varying the width W of the active layer, the path area (the cross-sectional area of the active layer) for the carriers, which cause the OFF current, varies.
However, when the thickness of the active layer was varied a noticeable variation in the value of the OFF current was seen, depending on this variation. It was thus confirmed that the OFF current is reduced by reducing the thickness of the active layer.
The abovementioned experimental fact results from the carrier movement, which is the cause of the OFF current, occurring mainly at the side face 24 of the active layer. Thus, if carrier movement, which is the cause of the OFF current, occurs mainly at the side face 24 of the active layer, then varying the width of the active layer will have almost no effect on the movement of carriers, and there will therefore be little variation in the value of the OFF current. On the other hand, reducing the thickness of the active layer reduces the carrier path, and therefore reduces the OFF current.
The reason that the carriers move via the side surface of the active layer results from the fact that a large number of traps concentrate at the side surface of the junction between the channel-forming region and the source region or the drain region. Traps concentrate at the side surface of the active layer for the following reason. In general, in order to form an active layer, a method employing dry etching, such as the RIE method, is used. In this case there is noticeable plasma damage at the peripheral edges and peripheral side faces of the active layer. Thus defects form in a concentrated manner at the side faces of the etched active layer. In other words traps concentrate at the side faces of the active layer.
In order to eliminate or reduce the traps which are present at the side faces of the active layer it is necessary to reduce the trap concentration by reducing the defects at the side face of the active layer after the patterning stage in which the active layer is formed (patterning by dry etching). In other words it is necessary to perform some type of annealing at the side surfaces.
The invention given in the present specification was performed by passing through the stages mentioned above.